FPGA Implementation of Modular Multiplication for Cryptographic Applications

Abstract

One of the most computationally expensive arithmetic operation's is modular multiplication. To create a realistic public-key cryptosystem, efficient algorithms and implementations are needed. Based on different integer lengths many algorithms of modular multiplication are implemented for public-key cryptosystems. Each implementation is efficient in parameters like power, area delay and high throughput. With the recent works on Verifiable Delay Functions (VDF's) the need for modular multiplication implementations to have the lowest possible latency has increased, as before low latency was not important as of high throughput in these multiplications. VDF's are designed to realise the underlying calculation in a predetermined amount of time that can be publicly validated. Inherently sequential arithmetic operations are used in VDF constructions. Recently, efficient VDF constructions based on Rivest, Shamir, and Wagner's time-lock puzzles have been suggested. For these VDF constructions, an RSA group exponentiation operation must be realised. Low-latency circuit implementation is proposed in this paper, along with an optimized FPGA version of the algorithm. © 2022 IEEE.