.svg)
Analysis of DRV trade-off in deep sub micron sram technology for low power
| dc.contributor.author | Singh S.K.; Kaushik B.K.; Chauhan D.S.; Chaurasia N.K. | |
| dc.date.accessioned | 2025-05-24T09:20:39Z | |
| dc.description.abstract | This paper presents different Data Retention Voltage (DRV) minimization techniques of six transistors SRAM cell for its proper working in a continuous technology scaling environment and for low power applications. The paper also explains the trade-off of all the techniques to better understand the applications for which those techniques can be utilized. © IDOSI Publications, 2014. | |
| dc.identifier.doi | https://doi.org/10.5829/idosi.wasj.2014.31.01.792 | |
| dc.identifier.uri | http://172.23.0.11:4000/handle/123456789/14278 | |
| dc.relation.ispartofseries | World Applied Sciences Journal | |
| dc.title | Analysis of DRV trade-off in deep sub micron sram technology for low power |