FPGA Implementation of Chaos based Pseudo Random Number Generator

Abstract

A PRNG (pseudo-random number generator) is proposed in this paper. The algorithm which is proposed here is dynamically adjusts the chaotic system's parameters to keep the device from falling into short-duration orbits and to make the formed sequences more random. This PRNG is implemented with a fixed point precision of 32-bit using Xilinx Vivado Design Suite Version 2019.2. By checking the randomness of the proposed PRNG to the sequences created by a Standard RNG(using $urandom) of size 32-bit, the proposed PRNG achieves significantly better randomness. Later, the following bitwise dynamical pseudo-random number generator is compared to standard randomization realizations using Monobit test Method which is used to check randomness. © 2021 IEEE.