BIST power minimization by transition reduction-a review

Abstract

The widespread use of battery-powered CMOS-VLSI devices in portable communication and computing equipments necessitated shift in the emphasis of designing built-in self-test (BIST) for VLSI from high fault coverage to low power dissipation during test mode. This requires addressing power dissipation issues at initial synthesis stage of circuit design and technology mapping is used for achieving low power dissipation. The excessive power dissipation in test mode could not only be prohibitive for field-testing with limited power budget but it can permanently damage the device or increase its downtime due to faster power supply drain. As a result, minimizing BIST power dissipation has been a challenging issue in VLSI design. This paper presents a review of the existing techniques for minimizing BIST power dissipation by reducing switching activity in digital CMOS circuits. The merits and limitations of major lowpower BIST techniques with reference to minimization of switching transients, fault coverage and affordable hardware and time overheads are discussed.