Design of registers and memory in QCA

dc.contributor.author	Sasamal T.N.; Singh A.K.; Mohan A.
dc.date.accessioned	2025-05-23T11:30:28Z
dc.description.abstract	In this chapter, we consider the design of sequential circuits in QCA. In particular, we presented the design of different D flip-flops and RAM cell with set and reset ability in QCA. The analysis for the proposed designs is carried out using rotated majority gate (MV3) and an efficient 5-input majority gate (MV5). © Springer Nature Singapore Pte Ltd 2020.
dc.identifier.doi	https://doi.org/10.1007/978-981-15-1823-2_8
dc.identifier.uri	http://172.23.0.11:4000/handle/123456789/12217
dc.relation.ispartofseries	Studies in Computational Intelligence
dc.title	Design of registers and memory in QCA

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