Design of DRAM sense amplifier using 45nm technology - Kumar A.; Pandey A.; Sahu P.K.; Chandra L.; Dwivedi R.; Mishra V.N. (My University, 2025)
In very large scale integration (VLSI) circuits, power consumption plays a crucial role to design memory elements and digital systems. This work proposed the power savings in DRAM sense amplifier can be done by using FSPA-VLSA (Foot Switch PMOS Access Voltage Latch Type Sense Amplifier). Applying this technique in open bit architecture of DRAM Cell during read operation, a reduction in overall power consumption has been obtained approximately 81%. The proposed circuit also has advantages in low power VLSI/ULSI design. The circuit has been designed and implemented in Cadence virtuoso tools at 45nm Technology. © 2018 IEEE.