Time-Sliced Architecture for Efficient Accelerator to Detrend High-Definition Electroencephalograms - Mittal R.; Amalin Prince A.; Fredo A.R.J. (My University, 2025)
Measuring electroencephalography (EEG) signals has a variety of important applications. Most processing systems use statistical machine learning algorithms. To increase accuracy of such systems, more data are measured in the form of increased channel count, called high-definition EEG (HD-EEG). EEG processing is hampered by noise from different instruments. While traditional detrending algorithms are highly resource-intensive, the problem is compounded for HD-EEG detrending. The generic-compounding architecture is not scalable. In such an architecture, one instance of the hardware accelerator is used for each channel. This is unsuitable for wearable devices which have limited computational and energy resources. In this article, we propose a time-sliced architecture to optimize resource and power utilization for a multi-channeled system. This is accomplished using time-division multiplexers and demultiplexers to share resources between different channels. The adaptive maximum-mean-minimum (AMaMeMi) filter is a computationally efficient algorithm, reported earlier for detrending EEGs. We apply guidelines of the proposed architecture, on the AMaMeMi filter, to design an efficient HD-EEG detrending hardware accelerator. The proposed accelerator is implemented for various channel counts. We use the Xilinx field-programmable gate array with part number XC7VX980T-1FFG1930 for implementation. We verify the correctness of the proposed architecture by comparing its output with that of the generic-compounding architecture. For a 1024-channeled system, the proposed time-sliced architecture provides 99% reduction in lookup table utilization, 70% in flip-flop utilization, 95% in area utilization, and 70% in estimated power utilization. © 1963-2012 IEEE.