Performance Analysis of Five Level Reduced Device Count AC-DC Converter

Abstract

In this work, a reduced device count five-level high power factor converter is presented. The proposed configuration is modeled as similar to conventional multi-point clamped multi-level converters. The well-established multi-level modulation techniques are also valid for the proposed power conversion stage to get the desired outcome. However, The PFC converter required fewer power semiconductor devices than its counterpart. In addition, the total topology requires minimum voltage blocking, which results in reduced cost, an increase in efficiency, and high power density. The performance validation is carried out with simulation as well as experimentation with laboratory prototype. © 2023 IEEE.