Junction Less Ferroelectric FET on FDSOI for Non-Volatile Logic-In-Memory Applications

Abstract

Ferroelectricity in HZO-based thin films and its integration of ferroelectric field effect transistors (FeFET) into standard CMOS platforms has germinated new prospects in the field of non-volatile memory and non-volatile computing. The FeFET has emerged from a theoretical concept to many experimental demonstrations in recent years. FeFETs can be widely used in a variety of fields, including non-volatile memory, neuromorphic computing, logic-in-memory (LiM), and others. This paper proposes a novel silicon-on-insulator (SOI) based junction-less ferroelectric field effect transistor (JLFeFET). Further, an investigation of a non-volatile latch for non-volatile logic-in memory computing is also done using the proposed JLFeFET. The proposed JLFeFET offers huge possibilities for the design of low-power and high-speed non-volatile logic-in-memory applications. Using the TCAD simulations, JLFeFET of 20 nm HfO2 thickness has been demonstrated that achieves a memory window (MW) of 0.34 V. The fabrication flow is also proposed with an easy integration of the JLFeFET device in silicon-on-insulator (SOI) process. Further, the proposed non-volatile latch with JLFeFET displays significantly low power with respect to its non-volatile counterpart implemented using magnetic tunnel junction (MTJ) devices. © 2022 IEEE.