Enhancing the Reliability of Hybrid MTJ/CMOS Circuits with Auto Write Termination

Abstract

Magnetic tunnel junction (MTJ) is a commercially attractive choice for the non-volatile memory and hybrid MTJ/CMOS logic circuits due to their notable features, including non-volatility, scalability, low power, high speed, and 3D integration with CMOS. Despite this, process variation and stochastic switching pose a significant barrier to the commercialization of MTJs due to reliability concerns. In this work, we have improved the MTJ's reliability by incorporating the auto-write termination (AWT) scheme into the conventional writing circuits. Here, writing/switching failures are used to define reliability. The conventional four-transistor (4T) write circuit with the proposed AWT circuit enhances the reliability of MTJs by continuous monitoring of the writing/switching operation and prevents redundant MTJ writing, thereby reducing the write failures significantly. The AWT scheme reduces the write failures by almost 99% less, as compared to the conventional write circuit. © 2023 IEEE.