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Algorithm for reduced order modelling of digital controllers
| dc.contributor.author | Sahani A.K.; Nagar S.K.; Pal Jayanta | |
| dc.date.accessioned | 2025-05-24T09:55:33Z | |
| dc.description.abstract | An algorithm for designing reduced order digital controller which can replace an existing high order cascade digital controller is presented. The parameters of the reduced order controller are obtained by applying frequency response technique. The new algorithm is illustrated by some examples. | |
| dc.identifier.doi | DOI not available | |
| dc.identifier.uri | http://172.23.0.11:4000/handle/123456789/19961 | |
| dc.relation.ispartofseries | Proceedings of the IEEE International Conference on Industrial Technology | |
| dc.title | Algorithm for reduced order modelling of digital controllers |