Novel Approaches for Designing Reversible Counters

Abstract

Reversible logic offers an alternative computation for future low-power computing devices. In this paper, an efficient and potent universal 33 and 44 reversible gates are considered to implement 4-bit counter. Performance of the proposed 33 gate is verified using thirteen standard three variables Boolean functions, which demonstrate from 17.8 to 45.2% superiority in term of gate counts obtained with other reversible gates. New structures for T flip-flop and D flip-flop, which utilize two efficient reversible gates are presented. These flip-flops and some existing gates are utilized to implement the Mod-16 counter and 4-bit Up/down counter. The reported architectures are modeled using VHDL and functional simulations are done using ISIM. © 2020, Springer Nature Singapore Pte Ltd.