TCAD Assessment Based Device to Circuit-Level Performance Comparison Study of Source Pocket Engineered All-Si Vertical Tunnel FET and GaSb/Si Heterojunction Vertical Tunnel FET

Abstract

In this work device to circuit-level performance comparison is made between GaSb/Si heterojunction vertical tunnel FET and all-Si vertical tunnel FET. A thin layer of heavily doped region (source pocket) is sandwiched between source and channel in the presented tunnel FETs to improve sub-threshold performance. GaSb as a low bandgap material is considered in the source region of the proposed tunnel FET to enhances the tunneling rate of the carriers by reducing the tunneling width of tunnel FET at source-channel junction. In the beginning, device parameters are optimized and simulations results of I-V and C-V characteristics are extracted from SILVACO ATLAS™ TCAD tool. These extracted parameters are than used to form 2D look up tables. Verilog-A based model has been formed using 2D look up tables and implemented in Cadence platform to design a digital logic inverter. © 2020 IEEE.