FPGA Implementation of Inversion in Galois Field Over GF(2m) with FLT and ITA Using Quad Blocks

Abstract

Many cryptographic algorithms and error-correcting codes use the Galois field inversion as a fundamental operation. One of the steps in these algorithms is to calculate the multiplicative inverse of a given element in the Galois Field. Numerous methods, such as Fermat's Little Theorem (FLT) and Itoh Tsujii Algorithm (ITA) can be used to efficiently perform the Galois field inversion operation. However, hardware implementation of Galois field inversion is a tedious task which demands extensive logic resources and execution time. In this paper, we have proposed a hardware architecture to perform multiplicative inversion operation in a Galois Field on an FPGA. We used QUAD blocks based on Brauer addition chain and demonstrated 13.2 % reduction in total number of L UTs required to implement the design as compared to the SQUARER method. © 2023 IEEE.