Performance Comparison of Ge/Si Hetero-Junction Vertical Tunnel FET with and without Gate-Drain Underlapped Structure with Application to Digital Inverter

Abstract

In this work, device-level to circuit-level assessment for a vertical Ge/Si heterojunction vertical tunnel field effect transistor (TFET) with and without gate-drain underlap structure has been reported. A source pocket is considered in between source and channel for both the structure to enhance the performance of the device. The effect of gate-drain underlap on gate to drain parasitic capacitance (Cgd) is analyzed. The performance in terms of IONIOFF and SS are investigated for the proposed devices. Gate-drain underlapped Ge/Si heterojunction vertical TFET is used to achieve better cut-off frequency and maximum frequency at VDS=0.5\V which is essential for RF applications. The DC and transient response of a digital inverter circuit based on proposed devices have been analyzed using Verilog-A model in the CADENCE tool. © 2020 IEEE.