Effects of source/drain elevation and side spacer dielectric on drivability performance of non-abrupt ultra shallow junction gate underlap GAA MOSFETs

Abstract

Present work focuses on quantitative effects of source/drain elevation height (h SD) and side spacer dielectric material (Air, SiO2, Si3N4 and HfO2) on the current drive of non-abrupt ultra shallow junction (USJ) gate all around (GAA) MOSFETs. It has been observed that the desirable unanimous reverse trend (increase in I on and decrease in I off with increase in source/drain elevation height (h SD) and/or side spacer dielectric constant, ε sp). Utmost percentage improvement in I on/ I off ratio at hSD=30.5nm and σL=7nm is found to be ~3000% for HfO2 while least as ~449% for Air with respect to their corresponding values at zero elevation. Thus, the increase in source/drain elevation with proper selection of side spacer is found to be a suitable approach. This will enhance the drivability as well as lower parasitic resistance in comparison to non elevated GAA MOSFETs at sub 20 nm technology node. © 2017, Indian Association for the Cultivation of Science.