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Design of a high gain low noise amplifier using 0.18μm CMOS technology
| dc.contributor.author | Ratan S.; Mondal D.; Anima R.; Kumar C.; Kumar A.; Jarwal D.K.; Mishra A.K.; Upadhyay R.K.; Kar R. | |
| dc.date.accessioned | 2025-05-24T09:31:59Z | |
| dc.description.abstract | In this paper, a high gain fully integrated low noise amplifier (LNA) that operates in 2.44GHz is designed using 0.18μm CMOS technology. This LNA is designed to be used in receivers of wireless communication systems. The circuit operates at 1.8V supply voltage. This circuit provides a high voltage gain of 38.63dB, power gain of 14.16dB and very low noise figure of 0.95dB. Here, S parameters are analyzed in detail to determine the value of S11 as -17dB and S12 as -44.14dB. The value of third order input referred intercept point is -3.045dBm, which provides stability of the circuit. The designed circuit dissipates very low power of 3.55mW. © 2018 IEEE. | |
| dc.identifier.doi | https://doi.org/10.1109/ICMETE.2018.00074 | |
| dc.identifier.uri | http://172.23.0.11:4000/handle/123456789/17606 | |
| dc.relation.ispartofseries | Proceedings - 2nd International Conference on Micro-Electronics and Telecommunication Engineering, ICMETE 2018 | |
| dc.title | Design of a high gain low noise amplifier using 0.18μm CMOS technology |