Design of Single-Bit Fault-Tolerant Reversible Circuits
| dc.contributor.author | Gaur H.M.; Singh A.K.; Mohan A.; Fujita M.; Pradhan D.K. | |
| dc.date.accessioned | 2025-05-23T11:26:43Z | |
| dc.description.abstract | This article introduces redundant design approaches for reversible circuits (RCs) that have the ability to detect and tolerate single-bit fault without the need of conventional voting scheme. Experiments preformed show that the proposed scheme reduces the gate cost on average with up to 28% as compared with tri-modular redundant circuits. RCs have direct relation with quantum computation which are largely to loss of energy levels due to the phenomenon of quantum decoherence that cause single point failures. | |
| dc.identifier.doi | https://doi.org/10.1109/MDAT.2020.3006808 | |
| dc.identifier.uri | http://172.23.0.11:4000/handle/123456789/10630 | |
| dc.relation.ispartofseries | IEEE Design and Test | |
| dc.title | Design of Single-Bit Fault-Tolerant Reversible Circuits |