Non-Volatile Latch Compatible with Static and Dynamic CMOS for Logic in Memory Applications

Abstract

To overcome the performance bottleneck of the CMOS-only logic circuits, logic-in-memory (LiM)-based circuits can be used. Herein, the memory and logic are combined to reduce the power requirements and the data access delay. The LiM architecture is proposed to be better in terms of efficiency when compared to the Von-Neumann architecture which is currently being used. In this article, a novel non-volatile (NV) latch is proposed to realize the LiM-based computation. It is compared with previous circuit architectures of the NV latch. The proposed latch consists of multiple magnetic tunnel junctions (MTJs) connected in series which are accessed through an NMOS transistor for reading the data. A cross-coupled inverter (CCI) is used to regenerate the output to the appropriate logic levels using its inherent regenerative action. The proposed latch has a simple design, higher stability, and lower tunnel magnetoresistance (TMR) degradation, and compatibility with static and dynamic CMOS logic styles. Furthermore, the proposed latch is having fewer transistor count in logic implementation which result in minimized area overhead and lower power consumption. The existing write circuit is also modified for writing the MTJs in the proposed NV latch which results in a 29.57% reduction in power consumption for a write margin of 20 μ A and 34.92% for 40 μ A write margin. Furthermore, the area requirement of the modified write circuit is found to be significantly lower than that of the existing write circuit. © 1965-2012 IEEE.