A Deep Insight into Frequency and Voltage Variation Impact on Memristor Performance and Applications of Memristor-NMOS Hybrid Structure in the Digital Domain

Abstract

This work investigates the effect of voltage and frequency variations on the hysteresis curve of the non-linear memristor model developed in the LTspice tool with different window functions namely Joglekar, Prodromakis, and Jinxiang. The methods to improve the hysteresis loop at higher frequency have been postulated. The usefulness of the memristor has been explored in the CMOS-based logic gates by replacing the bulk PMOS with a memristor to reduce their size and improve the performance without much compromising on parameters like delay and power consumption at different frequency ranges. In addition, the implementation of a hybrid CMOS-Memristor-based SRAM cell has been made and a comparative study on delay and noise margin analysis during both read and write operations concerning the traditional 6T CMOS-based SRAM cell has been carried out. The memristor modelling and circuit implementation have been carried out in the LTspice tool with TSMC 180nm technology node. © 2024 IEEE.