Optimized - Block based trace cache

Abstract

Multiple-block prediction has been an exciting research area in the vast expanse of computer architecture. Block based trace cache was a valid proposal to feed the execution units with enough instructions so that the utilization of the execution units is to the fullest in a superscalar architecture. The block based trace cache aligns and stores instructions at the basic block level instead of at the trace level, thus significantly reducing instruction trace storage requirement [5]. This paper investigates an optimization strategy that could be adopted to shrink the power consumed by a typical block based trace cache at the same time speeding up the process. A basic 5-stage pipelined architecture is considered here. The proposed design was tested using the SPEC2006 benchmark suite. © 2013 IEEE.