Evaluation of threshold voltage for 30 nm symmetric double gate (SDG) MOSFET and it's variation with process parameters

Abstract

In this paper, the evaluation of threshold voltage design parameters for 30 nm lightly doped nanoscale Symmetrical Double Gate (SDG) MOSFET is carried out based on an analytical solution of potential and threshold voltage with two dimensional Poission's equation. In this paper the threshold voltage is taken as function of the design parameters of the device such as channel length, drain source voltage, channel doping density, channel thickness and oxide thickness. The paper shows that the analyticaly expression developed for threshold voltage is the function of the distance along the channel length and hence using the concept of minimum surface potential along the channel length at the interface of Si/SiO2 of top and bottom gates the uniformity of threshold voltage along the longitudinal direction is maintained. For the analysis of threshold voltage design parameters, the impact of the substrate doping concentrations, channel length, channel thickness and oxide thickness on threshold voltage is carried out extensively to achieve optimim value of the device parameters for the actual fabrication of the device based on ITRS-2006. The variation of oxide thickness on threshold voltage Roll-off is also shown in this paper. The simulation of the SDG MOSFET is carried out with the device simulator ATLAS for the evaluation of design parameters for an optimized operation of the device. Copyright © 2008 American Scientific Publishers All rights reserved.