Effects of Elevated Source/Drain and Side Spacer Dielectric on the Drivability Optimization of Non-abrupt Ultra Shallow Junction Gate Underlap DG MOSFETs

Abstract

The effects of drain/source elevation height (hSD) and side spacer dielectric between the gate and source/drain regions on the drivability performance of the non-abrupt ultra-shallow-junction gate underlap double gate metal oxide field effect transistor of 18 nm gate length has been investigated in terms of the on-state (Ion), off-state (Ioff) drain currents, and Ion/Ioff ratio. Among the Air, SiO2, Si3N4 and HfO2 used as spacer dielectrics, while both Ion and Ion/Ioff are increased with the elevation height (hSD) and permittivity of the spacer dielectric, interestingly, an inverse relation between the Ion and Ioff for all hSD below ∼32.5 nm is observed only for the SiO2 spacer dielectric. Another new observation is the increase in Ioff with the hSD and permittivity of the spacer dielectric due to the enhancement of gate-induced drain leakage current owing to the increased vertical electric field at the drain side. For the most commonly used dielectrics SiO2 and HfO2 in the spacer region, the Ion/Ioff ratio is increased by ∼277% (at hSD = 32.5 nm) and ∼516% (at hSD = 9.5 nm) with respect to their corresponding values at zero elevation, respectively. © 2016, The Minerals, Metals & Materials Society.