Simulation of CMOS Inverter Circuit and 1-Bit Magnitude Comparator Circuit Utilizing Low-Voltage Flexible TFTs

Abstract

The article presents the implementation of a complementary metal-oxide-semiconductor (CMOS) inverter circuit using low-voltage, flexible thin-film transistors (TFTs). In this design, amorphous indium gallium zinc oxide (a-IGZO) is utilized as the n-channel TFT (n-TFT), while PBTTT-C14 is employed as the p-channel TFT (p-Tft). Both TFTs were previously fabricated and simulated, demonstrating operation at low voltages of 1V and 2V, respectively. These TFTs were compactly modeled using the Silvaco Techmodeler tool and subsequently integrated into the Silvaco Gateway platform for the realization of the CMOS inverter circuit and a 1-bit magnitude comparator. The CMOS inverter circuit exhibits favourable characteristics, including a high logic swing of 2V, a significant gain of 9.1, and a minimal average propagation delay of 3.15 ns. Additionally, using this CMOS logic with the aforementioned low-voltage TFTs, a 1-bit magnitude comparator was implemented with the Silvaco Gateway tool, demonstrating excellent transient behavior under various test conditions, such as (A > B, A < B and A=B). This CMOS logic framework holds significant potential for further applications in the development of more complex analog, digital, and memory circuits. © 2024 IEEE.