Study of role of channel engineering and gate engineering in silicon-on-insulator (SOI) MOSFETs using 2-D analytical modeling

dc.contributor.author	Goel V.; Maurya A.K.; Sharma S.; Kumar S.
dc.date.accessioned	2025-05-24T09:29:54Z
dc.description.abstract	This paper presents an overview of effects of channel and gate engineering separately on single gate fully depleted silicon-on-insulator (SOI) MOSFETs. Analytical surface potential models for graded-channel (GC) and dual-material-gate structures, each representing the effect of channel engineering and gate engineering respectively, have been developed to study the figure of merit of different structures over SOI MOSFETs. For validation, results obtained from analytical model have been compared with numerical simulation data obtained by 2-D device simulator, ATLAS™ SILVACO. © 2016 IEEE.
dc.identifier.doi	https://doi.org/10.1109/ICEmElec.2016.8074580
dc.identifier.uri	http://172.23.0.11:4000/handle/123456789/16428
dc.relation.ispartofseries	2016 3rd International Conference on Emerging Electronics, ICEE 2016
dc.title	Study of role of channel engineering and gate engineering in silicon-on-insulator (SOI) MOSFETs using 2-D analytical modeling

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