A Proposed Fully Transparent, Flexible, and Compact Modeled Low-Voltage TFT for Implementation of Full Adder and Subtractor

Abstract

In this article, a low-voltage, fully transparent, flexible thin-film transistor (TFT) is simulated using the Silvaco-Atlas tool, in which amorphous indium-gallium–zinc oxide (a-IGZO) and HfO2 are used as the active layers, gate dielectrics of the TFT, and indium-tin oxide (ITO) serves as the electrodes for source, drain, and gate contacts. In addition, this TFT is compactly modeled and used in the implementation of full adder and full subtractor circuits through the Silvaco-Techmodeler and Silvaco-Gateway tools. The technology computer-aided design (TCAD) simulated device has an operating voltage of 2 V and good performance parameters, such as a low threshold voltage of 0.104 V, high mobility (~8.9 cm2/V-sec), high ION / IOFF~105} , and a low subthreshold slope (SS) of 65 mV/decade. The Silvaco-Gateway tool is used for the execution of full adder and subtractor circuits. For all eight inputs (from 000 to 111), it gives quite acceptable transient characteristics in analyzing corresponding outputs as sum, carry, difference, and borrow. Silvaco-Techmodeler tools help in the compact modeling of simulated devices and generate a high level of accuracy of ~100% with very minimal error between simulated and modeled data (0.41% and 0.94%, respectively). This simulated, compactly modeled TFT would be used in the near future for analyzing complex analog and digital circuits. © 2024 IEEE.