ABACa: Access based allocation on set wise multi-retention in STT-RAM last level cache

Abstract

Exhibition of potential advantages of high density, non-volatility, and low static power consumption makes STTRAM a credible successor to SRAM in caches. However, higher write energy and latency of the STT-RAM limit its potential towards commercial usage. Relaxation of STT-RAM's retention time can be a viable solution to alleviate these obstacles by reducing both write time and energy. However, significant reduction in retention time might lead to premature expiry of the blocks requiring frequent refreshes or write-backs, which can incorporate unnecessary stalls along with the increased miss-rate.This paper proposes ABACa, an approach that logically bifurcates a cache set-wise for two different retention times where cache blocks are segregated upon their arrival and placed in the corresponding set, accordingly. In particular, if a block's arrival is triggered by a read miss, the block is placed into a set with a higher retention time, called as read-set. On the other hand, the block is placed into a write-set having a lower retention time, if the block's arrival is caused by a write miss. Our empirical analysis shows that, ABACa achieves a significant improvement of 40.75% in miss-rate and 61.35% EDP (Energy Delay Product) gain compared to baseline multi-retention STT-RAM-based and SRAM-based last level caches, respectively. © 2021 IEEE.