Controller synthesis for the under-load tap-changing transformer problem - A timed discrete event systems approach

Abstract

Discrete-event models are generally used to describe systems where coordination and control is required to ensure the orderly flow of events, or to avoid the occurrence of certain chains of events. This paper discusses the plant generator as well as the specification generated in timed mode. It approaches to synthesize the controller/supervisor with timed constraints of the plant generator as well as the specification generated (in timed mode) when timing is enforced from outside in the absence of the "breakdown event". The supervisory controller synthesis is mentioned under the Ramadge-Wonham (RW) framework for the voltage control problem in a power system network component i.e. ULTC (Under load tap changing transformer) in automatic mode of operation. The designed controller is simulated and analyzed under TTCT (timed toy control theory) software.