Back gated strained-Si (s-Si) on silicon-germanium-on-insulator (SGOI) MOSFETs for improved switching speed and short-channel effects (SCEs)

Abstract

The present work focuses on Figure-of-merit (FOM) of strained-Si-on- Silicon-Germanium-on-Insulator (SSGOI) MOSFETs with back gate configuration in terms of drain-induced-barrier-lowering (DIBL) and subthreshold swing (S). The theoretical model is developed by solving the 2D Poisson's equation with suitable boundary conditions using evanescent mode analysis technique in both the strained-Si and relaxed Si1-xGex layers. We have studied the effect of buried oxide thickness on DIBL and subthreshold swing. The validity of analytical model is verified by using ATLAS™, a 2D device simulator from Silvaco. © 2013 AIP Publishing LLC.